基于Innovus工具的28 nm DDR PHY物理设计方法

王秋实; 张  杰; $2

引用本文:	王秋实，张杰，孟少鹏. 基于Innovus工具的28 nm DDR PHY物理设计方法[J]. 雷达科学与技术, 2020, 18(4): 457-460.[点击复制]
	WANG Qiushi， ZHANG Jie， MENG Shaopeng. Physical Design Methods of a 28nm DDR PHY Based on Innovus[J]. Radar Science and Technology, 2020, 18(4): 457-460.[点击复制]

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基于Innovus工具的28 nm DDR PHY物理设计方法
王秋实，张杰，孟少鹏
中国电子科技集团公司第三十八研究所，安徽合肥230088

摘要:

随着CPU、DSP等器件的处理速度迅速提高，对内存的速度和各方面的需求迅速增加。早期的SDRAM工作频率发展到133MHz已到极限，成为系统性能的瓶颈。DDR（双倍数据率）技术随之应运而生，目前DDR4的性能已经可以达到3200Mbps级别。DDR PHY作为存储控制器和DRAM颗粒物理接口之间的通用接口，是制约DDR读写速度提升的关键。本文以TSMC 28nm工艺的DDR PHY设计为例，结合Innovus工具，在描述流程之外，重点研究解决了后端物理设计中时序路径的时间预算、延时优化、路径对齐等问题。最后该DDR PHY在一款工业级DSP中成功集成，并且板级测试结果表明其物理设计结果达到指标要求。

关键词: DDR PHY 物理设计 Innovus 时间预算延时优化路径对齐

DOI：DOI:10.3969/j.issn.1672-2337.2020.04.018

分类号:TN47

基金项目:

Physical Design Methods of a 28nm DDR PHY Based on Innovus

WANG Qiushi， ZHANG Jie， MENG Shaopeng

The 38th Research Institute of China Electronics Technology Group Corporation, Hefei230088, China

Abstract:

With the rapid increase in the processing speed of CPU and DSP, the demand for speed and other various aspects of memory has increased rapidly. The early SDRAM operating frequency has developed to the limit of 133MHz, which became the bottleneck of system performance. Afterwards, DDR (double data rate) technology came into being, and the performance of DDR4 can reach 3200Mbps. DDR PHY, as a common interface between the memory controller and high-speed DDR DRAM device, is the key to restricting the read-write speed. This paper describes physical design methods of a 28nm DDR PHY based on Innovus, with focus on timing budget, delay optimization and path balancing. Finally, this DDR PHY is integrated into an industrial DSP. The board-level test results show that the DDR PHY performance meets the requirements.

Key words: DDR PHY physical design Innovus timing budget delay optimization path balancing